1. Field of the Invention
The present invention relates to semiconductor memory devices, and more specifically to variable threshold voltage memory cells for use in a semiconductor memory device.
2. Description of Related Art
Most dynamic random access memory (DRAM) devices use memory cells that each consist of one transistor and one capacitor to store charge as an indication of the stored information (i.e., binary state). Conventional DRAMs utilize either trench capacitors, which are formed by digging deep into the substrate, or stack capacitors, which are fabricated above the surface of the substrate in the dielectric and interconnect region of the device. Additionally, conventional DRAMs are formed with some combination of poly-silicon for the plates of the capacitor and a nitrided oxide for the dielectric.
An essential requirement in scaling the area of DRAMs is a reduction in the area occupied by the transistors and capacitors of the memory cells. However, when reducing the area, the capacitor must be able to maintain approximately the same charge (typically 35-50 fC) and the transistor must maintain low currents (typically in the sub-fA range). More specifically, the amount of stored charge must remain constant while the area occupied by each capacitor decreases because of density demands. Likewise, the demand on the transistor's leakage current has become more stringent in order to prevent such leakage from occurring as the memory cell dimensions are reduced. Thus, the design of DRAMs having one transistor and one capacitor memory cells has become increasingly difficult.
Recently, it has been proposed to reduce the size requirements of the capacitors by replacing the conventional dielectric material with tantalum oxide, barium strontium titanate, or some other similar high dielectric material. However, the use of barium strontium titanate necessitates the use of specific noble metals such as platinum or conducting oxides such as iridium oxide. Other recent proposals reduce the memory cell dimensions by using a vertical structure that maintains low leakage while occupying a smaller area. For example, Pein et al. describe a reduced size EEPROM structure in H. Pein et al., "A 3-D sidewall flash EPROM cell and Memory Array", Tech. Dig. of IEDM 415 (1993), Hanafi et al. describe a reduced size, low power, high speed memory in H. Hanafi et al., "A Scalable Low Power Vertical Memory," Tech. Dig. of IEDM, 657 (1995), and a capacitor with vertical transistor cell is described by Sonouchi et al. in K. Sonouchi et al., "A Surrounding Gate Transistor (SGT) Cell for 64/256 Mbit DRAMs" Tech. Dig. of IEDM 23 (1989), which are herein incorporated by reference.